The invention generally relates to a preventive treatment process for the exclusion zone of a multilayer semiconductor wafer.
Processes for transferring layers to make multilayer structures from semiconductor materials are known. Conventional processes include creating a weakened zone within the thickness of a donor substrate, bonding the donor substrate to a receiving substrate, and detaching at the weakened zone. The weakened zone may be created in association with the creation of different layers at the surface of the donor substrate. Following detachment, at least one layer of the donor substrate can be transferred onto a receiving substrate. This type of process builds up wafers that may be, for example, of the SOI (Silicon On Insulator) type. Such a process can also be used to make other types of multilayer wafers. The wafer obtained may have one or several intermediate layers between the surface layer of the final wafer and the base layer that corresponds to the receiving substrate. Thus, an SOI may include an intermediate insulating layer (for example made of SiO2) between the receiving substrate and the silicon surface layer.
An example a transfer process is the SMART-CUT® process, and a description of the process can be found in a book entitled: “Silicon-On-Insulator Technology: Materials to VLSI, 2nd Edition” by Jean-Pierre Colinge, published by “Kluwer Academic Publishers”, at pages 50 and 51. This transfer process can be used to create multilayer wafers like those mentioned above. It can also be used to create wafers with an extremely thin surface layer having a thickness on the order of a few microns or less.
It is noted that the transfer of a layer during the detachment step could be accompanied by the formation of an approximately annular peripheral shoulder around the wafer. This shoulder is referred to as an exclusion zone because no bonding occurs in that area and subsequently no layer is transferred in that area. It has been observed that use of the SMART-CUT® type process can generate such areas. FIG. 1 shows this type of area about the edge of an SOI type wafer 10.
The wafer 10 includes a surface layer 101 (which usually corresponds to the useful layer of the wafer) made of monocrystalline silicon that overlaps an SiO2 layer 102. These two layers 101 and 102 are bonded to a layer 103 corresponding to the receiving substrate. The layer 103 may be made of polycrystalline silicon, for example. The layer 102 is an intermediate layer that has been inserted between the surface layer 101 of the wafer and its base layer 103. A exclusion zone 110 is also shown, and extends around the entire periphery of the wafer 10. The exclusion zone 110 results from the detachment of layers 101 and 102 from a weakened donor substrate.
FIG. 1 also shows that the intermediate layer 102 has an exposed peripheral edge 1020. Exposure of the peripheral edge of the intermediate layer 102 can have negative consequences, which will be explained below.
Complementary treatments are usually applied to the wafer after the detachment step. Complementary treatments are used to improve the surface condition of the wafer (particularly to reduce the surface roughness), or to modify the crystalline structure of one or several layers, or to reinforce the bond between the layers of the wafer. Such treatments may involve a chemical attack and/or heat treatment of the wafer. For example, the treatments may include a “stabox” step.
A “stabox” operation performed on a wafer is generally known in the art and corresponds to the following steps. The surface of the wafer is oxidized to create an oxide layer on the surface of the wafer that will protect the surface during the next heat treatment. Next, a heat treatment is used to stabilize the bonding interface. For example, annealing at a temperature on the order of about 1100° C. can be used for this purpose. Lastly, deoxidation of the oxide deposited on the surface of the wafer is carried out. For example, a chemical attack using an HF etching type solution could be used, with the HF solution having a concentration of about 10 to 20%.
When a “stabox” type operation is carried out on an SOI wafer like that shown in FIG. 1, the intermediate layer 102 of the wafer is attacked around its periphery. The result is shown in FIG. 2, wherein the layer 102 has been affected by removal of material towards the center of the wafer (towards the right in the drawing of FIG. 2). The removal of material results from an attack on the peripheral edge or belt around the layer 102 which was exposed by the etching solution used during the deoxidation operation. FIG. 2 also shows that the surface layer 101 overhangs the intermediate layer 102 due to the setback of the intermediate layer, because the side edge of the surface layer 101 extends beyond the edge of the intermediate layer 102. Such an overhanging configuration may be harmful. In particular, the overhanging portion 1010 of the layer 101 may collapse and/or break. If a piece of the overhanging portion 1010 detaches, it could adversely affect the wafer. For example, such a detached piece could be deposited on one of the faces of the wafer and cause surface deterioration (for example, by scratching it or remaining attached to it).
Semiconductor wafers are typically intended for use in electronics, microelectronics and optoelectronics, and must satisfy extremely strict surface condition specifications. The overhanging configuration illustrated in FIG. 2 would fail to satisfy such specifications.
FIG. 2 also illustrates an additional adverse effect resulting from the use of a “stabox” operation. In particular, the layers 101 and 102 are curved as the edges of these layers have been raised and separated from the base layer 103. This curvature corresponds to an additional effect of the “stabox” step, and includes a setback of the intermediate layer and the creation of an overhang. This additional effect is a consequence of the thermal stresses applied to the different layers of the wafer, particularly during the oxidation heat treatment of the wafer surface. Since the different layers in the wafer do not have the same coefficients of thermal expansion, the layers do not behave in the same way when they are exposed to a higher thermal budget. The result is a partial delamination of layers 102 and 103 at the edge of the layer 102. Furthermore, during the same oxidation heat treatment, the free space formed between the layers 102 and 103 due to the separation has been partially filled in by a new oxide 1021.
However, it is noted that this additional effect is not a major disadvantage. Shrinkage of the intermediate layer 102 is a more serious problem, which may be the result of a chemical attack on the wafer. It may also be the result of a different type of attack on the peripheral belt or edge around the intermediate layer which is sensitive to such an attack. If the wafer is subjected to a prolonged high temperature heat treatment, for example, in a furnace used to treat wafers in batches, then an attack occurs around the exposed periphery of an intermediate layer of oxide of an SOI structure. It may be desirable to perform such a heat treatment, for example, to modify the crystalline structure of some layers, or to reduce the surface roughness of the wafer.
Prolonged high temperature heat treatment is conventionally carried out within a hydrogen and/or argon atmosphere. The term “high temperature” means a temperature exceeding about 950° C. In addition, the term “prolonged” means a heat treatment applied for a duration of greater than a few minutes.
Another example of a treatment that causes problems like those mentioned above occurs when an additional “stabox” step is performed (for example on an SOI type wafer) after carrying out a first “stabox” step and polishing the wafer. A non-limiting example of such a treatment is described in International Application No. WO 01/15218, which describes a surface treatment of an SOI type wafer involving a sequence of stabox, polishing, and stabox type steps. The stabox process is disclosed in that document and can be referred to for further details, if necessary.
FIG. 3a diagrammatically shows an SOI structure on which a first stabox step was carried out. The edges of the layers 101 and 102 form a steep bevel following polishing. This bevel shape exposes the edge of the intermediate layer 102 to a greater extent than that shown in FIG. 1.
FIG. 3b shows the same SOI structure as FIG. 3a, on which a polishing step and then a second stabox step were conducted. The bevel shape has been modified by these new steps. But the intermediate layer 102 is still exposed, and is therefore still subject to attack by subsequent treatments that may be applied to the wafer. Thus, it is clear that some treatments (particularly chemical treatments, and/or prolonged high temperature heat treatments) applied to a multilayer wafer having an intermediate layer with an exposed peripheral edge may be detrimental.
Thus, there is a need for a treatment that can be applied to these wafers to protect the intermediate layer, and the present invention now provides this.